POUOST=Val_0x0, SPHEN=Val_0x0, HASHTBLSZ=Val_0x0, RAVSEL=Val_0x0, DCBEN=Val_0x0, L3L4FNUM=Val_0x0, AVSEL=Val_0x0, ADDR64=Val_0x0, ADVTHWORD=Val_0x0, OSTEN=Val_0x0, PTOEN=Val_0x0
ETH Hardware Feature Register 1
| RXFIFOSIZE | MTL Receive FIFO Size 4 (Val_0x4): 2048 bytes |
| SPRAM | Single Port RAM Enable 1 (Val_0x1): Single port RAM is enabled |
| TXFIFOSIZE | MTL Transmit FIFO Size 4 (Val_0x4): 2048 bytes |
| OSTEN | One-Step Timestamping Enable 0 (Val_0x0): One-step timestamping is disabled |
| PTOEN | PTP Offload Enable 0 (Val_0x0): PTP offload is disabled |
| ADVTHWORD | IEEE 1588 High Word Register Enable 0 (Val_0x0): IEEE 1588 high word register is disabled |
| ADDR64 | Address Width. 0 (Val_0x0): 32 |
| DCBEN | DCB Enable 0 (Val_0x0): DCB is not selected |
| SPHEN | Split Header Enable 0 (Val_0x0): Split header is disabled |
| TSOEN | TCP Segmentation Offload Enable 1 (Val_0x1): TCP segmentation offload is enabled |
| DBGMEMA | DMA Debug Registers Enable 1 (Val_0x1): DMA debug registers enabled |
| AVSEL | AV Enable 0 (Val_0x0): AV fature is disabled |
| RAVSEL | Rx Side Only AV Enable 0 (Val_0x0): Rx side only AV is disabled |
| POUOST | One Step for PTP over UDP/IP Enable 0 (Val_0x0): One step for PTP over UDP/IP is disabled |
| HASHTBLSZ | Hash Table Size 0 (Val_0x0): No hash table |
| L3L4FNUM | Total number of L3 or L4 Filters 0 (Val_0x0): No L3 or L4 filter |